Functional description

TDA7333N

14/36

3.5

Group and block synchronization module

The group and block synchronization module has the following features:

–

Hardware group and block synchronization

–

Hardware error detection

–

Hardware error correction, using quality bit information to indicate bad corrections

–

Hardware synchronization flywheel

–

TA, TAEON information extraction

–

Reset by software “ar_res”, which resets also RAM buffer addresses and RDS

demodulator

Figure 5.

Group and block synchronization diagram

This module is used to acquire group and block synchronization of the received RDS data

stream, which is provided in a modified shortened cyclic code. For theory and

implementation of modified shortened cyclic code and error correction, please refer to

CENELEC Radio Data System (RDS) specification EN50067.

Group and block synchronization module can detect and correct five bit error burst in the

data stream. If an error correction is done on a good quality marked RDS bit, the “data_ok”

bit rds_corrp[1] won’t be set (refer to page 22). Before error correction, the five MSBs of the

syndrome register are stored in the “cp” bits rds_corrp[7:3].

If the five LSBs of the syndrome register are zero, the “cp” pattern is used for error

correction. After that operation the syndrome must become zero for valid RDS data. The

S(4:0)

RDSCLK

RDSDAT

RDSQAL

rds_bd_h,rds_bd_l

rds_corrp

rds_qu

rds_int

RDSDAT(15:0)

Q(3:0)

CP(9:5)

Correct. pat.

Syndrome register

S(9:0)

Correction

logic

Corrected

Data_OK

Block

missed

QU(0:3)

RDS block counter

ABH

DBH

BLOCK E detected

Syndrom zero

Group & Block Synchronization Control Block

set

set

new

Block

available

next

RDS

bit

int

bit_int

res

AR_RES

read only

read only

read only

read/write

BLOCK A

Quality bit counter

from RDS

Demodulator

BLOCK B

BLOCK D

TAEON

TA