TDA7333N datasheet(25/36 Pages) STMICROELECTRONICS

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TDA7333N

Functional description

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3.8.9

pllreg4 register

3.8.10

pllreg3 register

3.8.11

pllreg2 Register

This bit is for internal test only.

PLL factional mode enable (10).

1: Fractional mode enabled.

0: Fractional mode disabled.

PLL fractional dither enable (10).

1: Fractional dither enabled.

0: Fractional dither disabled.

Power down mode.

0: Normal mode

1: Power down mode. All clocks are stopped. This mode can only

be exit by hardware reset.

PLL enable. If this bit is set the PLL will be initialized with the values

of the pllreg4-0 registers. After PLL locking, the system clock (fsys)

is switched to the PLL output clock which must be 8.55 or 8.664

MHz. Clearing this bit will switch fsys back to the XTI clock.

PLL lost lock.

This bit is set if the PLL is used and loses lock. It will be cleared if

the PLL is disabled and enabled again.

PLL lock.

1: PLL is currently locked.

0: PLL is currently out of lock.

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r/w

FRAEN

LOCK

PLLEN

LLOCK

DITEN

reset value

011

pllreg4

PWDN

TEST1 TEST0

bit 3 of PLL output divide factor (9) (10) (12).

bit 4 of PLL output divide factor (9) (10) (12).

bit 0 of PLL input divide factor (10) (12).

bit 1 of PLL input divide factor (10) (12).

bit 2 of PLL input divide factor (10) (12).

bit 3 of PLL input divide factor (10) (12).

bit 4 of PLL input divide factor (10) (12).

Not used.

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r/w

ODF3

ODF4

IDF2

IDF3

IDF4

IDF1

IDF0

reset value

001

pllreg3

(9) ODF value equal to zero is ignored, one is then used.

bit 2 of PLL multiplication factor (10) (11) (12).

bit 3 of PLL multiplication factor (10) (11) (12).

bit 4 of PLL multiplication factor (10) (11) (12).

bit 5 of PLL multiplication factor (10) (11) (12).

bit 6 of PLL multiplication factor (10) (11) (12).

bit 0 of PLL output divide factor (9) (10) (12).

bit 1 of PLL output divide factor (9) (10) (12).

bit 2 of PLL output divide factor (9) (10) (12).

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r/w

MF2

MF3

MF6

ODF3

ODF0

ODF1

MF5

MF4

reset value

010

pllreg2

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