Application information

L6591

14/32

Figure 6.

Timing diagram: normal power-up and power-down sequences

At converter power-down the system will lose regulation as soon as the input voltage is so

low that either peak current or maximum duty cycle limitation is tripped. Vcc will then drop

and stop IC’s activity as it falls below the UVLO threshold (10.5 V typ.). The Vcc_OK signal

asserted too and the HV generator is disabled. This prevents converter’s restart attempts

and ensures monotonic output voltage decay at power-down.

the L6591 will have a very low repetition rate, as shown in the timing diagram of Figure 7,

and that the converter will work safely with extremely low power throughput.

The restart threshold of the HV generator is changed when any latched disable function of

the IC is invoked to ensure a real latch-off. For more details see

“Latched shutdown” section.

 

Vcc

HVG, LVG

HV_EN

Vcc

off

Vcc

restart

t

t

t

t

Vin

0.75 mA

t

t

Vcc_OK

Power-on

Power-off

Normal

operation

regulation is lost here

PFC_STOP