TDA7590 datasheet(30/40 Pages) STMICROELECTRONICS

30 / 40 page

Appendix 1

TDA7590

30/40

; settings for the Bus Control Register

;

321098765432109876543210

INIT_BCR

EQU

%001100000010010000100001 ; 306E10

;INIT_BCR

EQU

%000001111111110011100111 ; 30FE07

;

00111 --- BA0W (Area 0 wait states)

;

00000 -------- BA1W (Area 1 wait states)

;

111 ------------- BA2W (Area 2 wait states)

;

111 ---------------- BA3W (Area 3 wait states)

;

00000 ------------------- BDFW (Default area wait states)

;

0 ------------------------ BBS

(0: ; 1: DSP is bus master READ ONLY)

;

0 ------------------------- BLH

(0: ; 1: BLN always asserted)

;

0 -------------------------- BRH

(0: ; 1: BRN always asserted)

;*******************************************************************************

; definitions addded by Paul Cassidy for salieri testbench

TRIGGER_TUBE

EQU

$12002

M_BCR

EQU

$FFFFFB

; Bus Control Register

M_AAR0

EQU

$FFFFF9

; Address Attribute 0

M_AAR1

EQU

$FFFFF8

; Address Attribute 1

M_AAR2

EQU

$FFFFF7

; Address Attribute 2

M_AAR3

EQU

$FFFFF6

; Address Attribute 3

;*******************************************************************************

;************************** Main Prog Starts Here ******************************

;*******************************************************************************

startp

org p:$0

jmp start

sci_int

org p:SCI_REC

; Interrupt SCI receive

jsr INT_SCIR

org p:SCI_TRANS

; Interrupt SCI transmit

jsr INT_SCIT

org p:SCI_REC_E

; Interrupt SCI framing error

jsr INT_SCIE

sai_int

org p:SAI_RDR

jsr INT_RDR

org p:SAI_TDE

jsr INT_TDE

org p:SAI_ROF

jsr INT_ROF

org p:SAI_TUF

jsr INT_TUF

essi_int

org p:essi0_rdf

jsr Comp_0

nop

org p:essi0_roe

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