ST6373 datasheet(45/64 Pages) STMICROELECTRONICS

45 / 64 page

ST6373

45/64

4.6 7-BIT PWM D/A CONVERTERS

The D/A peripheral features nine PWM D/A out-

puts (31.25kHz repetition, DA0-DA8) with seven

bit resolution.

Each D/A converter is composed by the following

main blocks:

- pre-divider

- 7-bit counter

- data latches and compare circuits

The pre-divider uses the clock input frequency

(8MHz typical) and its output clocks the 7-bit free-

running up-counter. The data latched in the DTOA

Data/Control Registers control the nine D/A out-

puts (DA0,1,2,3,4,6,7 and 8). When the values in

the counter and data latch are equal, the relevant

output is set. The output is reset on the counter

overflow. When a DTOA output is disabled (bit 7 of

corresponding Control Register is low) the output

is forced to zero whatever the value of bits 0 to 6.

When enabled (bit 7 = 1) the output depends on

bits 0 to 6. If all these bits are equal to zero the rel-

evant output is an high logic level. All 1’s corre-

spond to a pulse with a 1/128 duty cycle and al-

most 100% zero level.

The frequency of the PWM DTOA outputs is 31.25

KHz. The duty cycle of the DTOA outputs change

in steps of 250ns.

The repetition frequency is related to the 8MHz

clock frequency. Use of a different oscillator fre-

quency will result in a different repetition frequen-

cy. All D/A outputs are Push-pull with standard

current drive capability.

DTOA channels 0 to 7 are held in a bank of two

blocks of four registers selected according to the

status of DABS, bit 0 of the D/A Bank Register at

address E7h. DTOA channel 8 is directly ad-

dressed at address E4h without the need of the

D/A BANK REGISTER.

D/A BANK Register (DABR)

Address: E7h - Read/Write

Reset Value: 00h

D7-D1 = Not Used.

DABS. D/A BANK Selection, This bit is used to se-

lect one of the two banks of 4 bytes located at ad-

dresses E0h to E3h. Read/Write, 0 after Reset.

0 = Select Bank 0

1 = Select Bank 1

Bank 0 is used for the DA0 to DA3 Outputs. Bank

1 is used for the DA4 to DA7 Outputs.

Table 13. Channel Address Selection

D/A Data Control Registers (DDCR)

Address: E0h to E3h, E4h - Write only

Reset Value: 0XXXXXXXXb

ENx.Enable bit, Write Only, 0 after Reset.

0 = Disable Channel x

1 = Enable Channel x

DAxC6 to DAxC0: Data Control bits Channel x,

Write Only, Undefined after Reset.

4.6.1 Digital Outputs

The nine 7 bits PWM outputs can also be used as

simple outputs.

DABS

Bank Select

Address

Channel

Selected

E0h

DA0

E1h

DA1

E2h

DA2

E3h

DA3

EOh

DA4

E1h

DA5

E2h

DA6

E3h

DA7

E4h

DA8

DAxC6 DAxC5 DAxC4 DAxC3 DAxC2 DAxC1 DAxC0

DDC Bit 7

DDCR bits 0 to 6

Output State

don’t care

all zero

ST6373 데이터시트(PDF) 45 Page - STMicroelectronics

ST6373 데이터시트(HTML) 45 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

데이터시트 다운로드

링크 URL