ST6373 datasheet(46/64 Pages) STMICROELECTRONICS

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ST6373

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4.7 SERIAL PERIPHERAL INTERFACES

The ST6373 features two on-chip Serial Peripher-

al Interfaces (SPIs) for synchronous communica-

tion with other local control/interface devices. The

two SPIs are similar in basic function, however the

first contains additional logic and EEPROM mem-

ory to manage the VESA DDC data protocol

(DDC1, DDC2B and DDC2AB) transmission and

reception. Both SPIs can manage Standard shift

modes (in addition to I

2C mode), and Master/Slave

2C Modes.

The serial modes of the SPI are summarised in the

following table:

Table 14. SPI Modes

The maximum external clock and VSYNC clock

speed is 25kHz.

The I2C Data Hold Time is 250ns minimum.

As the I

2C SPI is derived from the DDC SPI, the

DDC SPI is shown, with the functional differences

shown.

For the DDC1 and DDC2B an additional 128 bytes

of dedicated EEPROM can be used to load the

SPI with predefined data automatically without any

CPU time consumption (see Block Diagram).

The Address Generator contains a 7-bits Auto-

Counter Register which allows the CPU to set a

EEPROM Start Address from 00h to 7Fh.

In DDC2B the Hardware Slave Address A0/A1h

can be enabled in parallel with the Programmed

I2C Slave Address.

Figure 29. DDC SPI Block Diagram

Slave Standard shift mode, with external

clock on EXTCLK

DDC SPI only

Master Standard shift mode with internal

clock

Both SPIs

DDC1 mode with VSYNC as clock

DDC SPI only

Multimaster/Slave

I2C mode

Both SPIs

VR02034

ADDRESS

SDAD

GENERATOR

ADDRESS

DATA

DDC EEPROM

DDC CONTROL

SHIFT

SCLD

VSYNC

AUTO

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