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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST70135 데이터시트(PDF) 18 Page - STMicroelectronics |
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ST70135 데이터시트(HTML) 18 Page - STMicroelectronics |
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18 / 29 page  ST70135A 18/29 The ST70135A samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted. TxClk, RxClk, AC Electrical Characteristics TxData, TxSOC, AC Electrical Characteristics RxData, RxSOC, RxClav AC Electrical Characteristics Symbol Parameters Min Max Unit F Clock frequency 1.5 25 MHz Tc Clock duty cycle 40 60 % Tj Clock peak to peak jitter 5% Trf Clock rise fall time 4 ns L Load 100 pF Symbol Parameters Min Max Unit T5 Input set-up time to TxClk 10 ns T6 Hold time to TxClk 1 ns L Load 100 pF Symbol Parameters Min Max Unit T7 Input set-up time to TxClk 10 ns T8 Hold time to Tx Clk 1 ns T9 Signal going low impedance to RxClk 10 ns T10 Signal going High impedance to RxClk 0ns T11 Signal going low impedance to RxClk 1ns T12 Signal going High impedance to RxClk 1ns L Load 100 pF Figure 15 : Timing (Utopia 1 Transmit Interface) Figure 16 : Timing Specification (Utopia 1) X H1 H2 P44 P45 P47 P48 X P46 TxCLK TxSOC TxENB TxDATA TxCLAV Clock Signal (at input) Signal (highz) T5, T7 T6, T8 T11 T9 T12 T10 |
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