ST7285C datasheet(95/117 Pages) STMICROELECTRONICS

부품명	ST7285C

상세설명	8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES

PDF	117 Pages

Scroll/Zoom	100%

제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

Logo

95 / 117 page

95/117

ST7285C

CONTROL TIMING (Cont’d)

1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge

the undefined region of the falling edge of SCL

2. The maximum hold time of the START condition only has to be met if the interface does not stretch the

low period of SCL signal

Cb = total capacitance of one bus line in pF

Figure 44. Definition of Timing Terminology

I2C BUS INTERFACE

Parameter

Standard I2C

Fast I2C

Symbol

Unit

Min

Max

Min

Max

Bus free time between a STOP and START

condition

4.7

1.3

Tubs

Hold time START condition. After this period,

the first clock pulse is generated

4.0

0.6

Thd:sta

µs

LOW period of the SCL clock

4.7

1.3

Tlow

µs

HIGH period of the SCL clock

4.0

0.6

Thigh

µs

Set-up time for a repeated START condition

4.7

0.6

Tsu:sta

µs

Data hold time

0 (1)

0.9(2)

Thd:dat

µs

Data set-up time

250

100

Tsu:dat

Rise time of both SDA and SCL signals

1000

20+0.1Cb

300

Fall time of both SDA and SCL signals

300

20+0.1Cb

300

Set-up time for STOP condition

4.0

0.6

Tsu:sto

Capacitive load for each bus line

400

Tbuf

Tlow Tr

Thd:sta

Tsp

Thd:sta

Thigh

Thd:dat

Tsu:dat Tsu:sta

Tsu:sto

SDA

SCL

ST7285C 데이터시트(PDF) 95 Page - STMicroelectronics

ST7285C 데이터시트(HTML) 95 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL