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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7285C 데이터시트(PDF) 116 Page - STMicroelectronics |
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ST7285C 데이터시트(HTML) 116 Page - STMicroelectronics |
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116 / 117 page  116/117 ST72E85 ST72T85 CONTROL TIMING (Cont’d) 1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 2. The maximum hold time of the START condition only has to be met if the interface does not stretch the low period of SCL signal Cb = total capacitance of one bus line in pF Figure 10. Definition of Timing Terminology I2C BUS INTERFACE Parameter Standard I2C Fast I2C Symbol Unit Min Max Min Max Bus free time between a STOP and START condition 4.7 1.3 Tubs ms Hold time START condition. After this period, the first clock pulse is generated 4.0 0.6 Thd:sta µs LOW period of the SCL clock 4.7 1.3 Tlow µs HIGH period of the SCL clock 4.0 0.6 Thigh µs Set-up time for a repeated START condition 4.7 0.6 Tsu:sta µs Data hold time 0 (1) 0 (1) 0.9(2) Thd:dat µs Data set-up time 250 100 Tsu:dat ns Rise time of both SDA and SCL signals 1000 20+0.1Cb 300 Tr ns Fall time of both SDA and SCL signals 300 20+0.1Cb 300 Tf ns Set-up time for STOP condition 4.0 0.6 Tsu:sto ns Capacitive load for each bus line 400 400 Cb pF Tbuf Tlow Tr Tf Thd:sta Tsp Thd:sta Thigh Thd:dat Tsu:dat Tsu:sta Tsu:sto SDA SCL |
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