ST92F124 datasheet(421/426 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - KNOWN LIMITATIONS

KNOWN LIMITATIONS (Cont’d)

The choice between Interrupt or DMA modes is

defined by the CP0D and CM0D bits (bit 6 and bit

3 in the IDMR register, R255 page 10/8).

CP0D : Capture 0 DMA Mask. Capture on REG0R

DMA is enabled when CP0D = 1.

CM0D: Compare 0 DMA Mask. Compare on

CMP0R DMA is enabled when CM0D = 1.

In DMA mode a DMA counter register and a DMA

address register define the location and the size of

the memory block (RAM or Reg. File) involved in

these transfers.

Each DMA transfer decreases the counter value.

When the counter reaches 0, an EndOfBlock

event occurs on the DMA controller. This event is

detected by the MFT which resets the CP0D or the

CM0D bit.

Limitation Description

If a MFT DMA request (for instance MFT1) occurs

when another peripheral DMA request is being

serviced (for instance MFT0), and if the MFT0

DMA corresponds to an End-of-Block, the MFT1

resets its DMA Mask bit even if the End-of-Block

signal is dedicated to the MFT0.

This limitation is due to wrong End-of-Block event

management by the MFT, it does not impact the

SCI and the I2C but they can be involved in the

limitation if:

– First peripheral requests a DMA transfer with

End-of-Block event,

– Other peripherals request a DMA transfer with a

higher priority level between the same two DMA

arbitrations. As a consequence, the MFT1 DMA

request is not serviced and a DMA transfer is

lost. This is also true for a Top Level Interrupt

(higher priority than DMA).

Arbitra-

MFT0

MFT1

End-Of

Output

Com-

pare

DMA

Request

DMA

Transfer

DMA

Transfer

End-of-Block

Interrupt

Routine

DMA

Request

The

Output

Compare

event generates an interrupt

and not a DMA request.

Interrupt

Request

Output

Compare

-Block

tion

CM0D

reset

CM0D

reset (1)

(1) The MFT1 CM0D bit should not be reset by the End-of-

Block signal unless its DMA request is being serviced.

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