ST92F120JR1T datasheet(301/320 Pages) STMICROELECTRONICS

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ST92F120 - ELECTRICAL CHARACTERISTICS

EXTERNAL BUS TIMING TABLE

(VDD =5V ± 10%, TA = –40°C to +105°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified)

Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,

prescaler value and number of wait cycles inserted.

The values in the right hand two columns show the timing minimum and maximum for an external clock at 24MHz, prescaler value of zero

and zero wait states.

Legend:

Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;

2 x OSCIN period when OSCIN is divided by 2;

OSCIN period x PLL factor when the PLL is enabled.

TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse width)

TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse width)

P = clock prescaling value (=PRS; division factor = 1+P)

Wa = wait cycles on

AS; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT)

Wd = wait cycles on

DS; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT)

Symbol

Parameter

Value (Note)

Unit

Formula

Min

Max

TsA (AS)

Address Set-up Time before AS

↑

Tck x Wa+TckH-9

ThAS (A)

Address Hold Time after AS

↑

TckL-4

TdAS (DR)

↑ to Data Available (read)

Tck x (Wd+1)+3

TwAS

AS Low Pulse Width

Tck x Wa+TckH-5

TdAz (DS)

Address Float to DS

↓

TwDS

DS Low Pulse Width

Tck x Wd+TckH-5

TdDSR (DR)

↓ to Data Valid Delay (read)

Tck x Wd+TckH+4

ThDR (DS)

Data to DS

↑ Hold Time (read)

TdDS (A)

↑ to Address Active Delay

TckL+11

TdDS (AS)

↑ to AS ↓ Delay

TckL-4

TsR/W (AS)

RW Set-up Time before AS

↑

Tck x Wa+TckH-17

TdDSR (R/W)

↑ to RW and Address Not Valid Delay

TckL-1

TdDW (DSW)

Write Data Valid to DS

↓ Delay

-16

TsD(DSW)

Write Data Set-up before DS

↑

Tck x Wd+TckH-16

ThDS (DW)

Data Hold Time after DS

↑ (write)

TckL-3

TdA (DR)

Address Valid to Data Valid Delay (read)

Tck x (Wa+Wd+1)+TckH-7

TdAs (DS)

↑ to DS ↓ Delay

TckL-6

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