13

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Burst Write Operation

The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The

address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The

subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any

additional data supplied to the DQ pins will be ignored.

1. The specific requirement is that DQS be valid(High or Low) on or before this CK edge.

The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.

0

1

2

3

4

5

6

7

8

CK

CK

Command

NOP

NOP

*1

NOP

NOP

NOP

NOP

NOP

DQS

DQs

Figure.6 Burst write operation timing

< Burst Length=4 >

WRITEA

WRITEB

Din 0 Din 1 Din 2 Din 3 Din 0

Din 2

Din 1

Din 3

*1