AT89C51CC03U-RDTIM datasheet(125/183 Pages) ATMEL

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125

AT89C51CC03

4182B–CAN–09/03

Functional Description

Figure 54 shows a detailed structure of the SPI Module.

Figure 54. SPI Module Block Diagram

Operating Modes

The Serial Peripheral Interface can be configured in one of the two modes: Master mode

or Slave mode. The configuration and initialization of the SPI Module is made through

two registers:

•

The Serial Peripheral Control register (SPCON)

•

The Serial Peripheral Status and Control Register (SPSCR)

Once the SPI is configured, the data exchange is made using:

•

The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-

pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows

individual selection of a Slave SPI device; Slave devices that are not selected do not

interfere with SPI bus activities.

Shift Register

Internal Bus

Control

Logic

MISO

MOSI

SCK

Clock

Logic

SPI Interrupt

8-bit bus

1-bit signal

FCLK

Receive Data Register

SPDAT

SPI

Control

Transmit Data Register

-MODF

SPIF

OVR

SPTE

UARTM SPTEIE MODFIE

SPSCR

SPEN

MSTR

SPR2

SSDIS

CPOL

CPHA

SPR1

SPR0

SPCON

Request

PERIPH

AT89C51CC03U-RDTIM 데이터시트(PDF) 125 Page - ATMEL Corporation

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