AT89C51CC03U-RDTIM datasheet(127/183 Pages) ATMEL

127 / 183 page

127

AT89C51CC03

4182B–CAN–09/03

Figure 56. Data Transmission Format (CPHA = 0)

Figure 57. Data Transmission Format (CPHA = 1)

Figure 58. CPHA/SS Timing

As shown in Figure 56, the first SCK edge is the MSB capture strobe. Therefore, the

Slave must begin driving its data before the first SCK edge, and a falling edge on the SS

pin is used to start the transmission. The SS pin must be toggled high and then low

between each Byte transmitted (Figure 58).

Figure 57 shows an SPI transmission in which CPHA is ’1’. In this case, the Master

begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first

SCK edge as a start transmission signal. The SS pin can remain low between transmis-

sions (Figure 58). This format may be preferred in systems having only one Master and

only one Slave driving the MISO data line.

Queuing transmission

For an SPI configured in master or slave mode, a queued data byte must be transmit-

ted/received immediately after the previous transmission has completed.

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

Capture Point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

567

Capture Point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

Byte 1

Byte 2

Byte 3

MISO/MOSI

Master SS

Slave SS

(CPHA = 1)

Slave SS

(CPHA = 0)

AT89C51CC03U-RDTIM 데이터시트(PDF) 127 Page - ATMEL Corporation

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