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V58C2256 데이터시트(PDF) 21 Page - Mosel Vitelic, Corp |
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V58C2256 데이터시트(HTML) 21 Page - Mosel Vitelic, Corp |
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21 / 61 page ![]() 21 MOSEL VITELIC V58C2256(804/404/164)S V58C2256(804/404/164)S Rev. 1.4 October 2002 Precharge Timing During Write Operation Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery require- ment. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a timing parameter (t WR) is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe in the last valid write data. “Write recovery” is complete on the next 2nd rising clock edge that is used to strobe in the Precharge command. Write with Precharge Timing (CAS Latency = Any; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 D0 D1 D2 D3 NOP Write NOP NOP NOP NOP PreA NOP CK, CK Command DQS DQ tRAS(min) tRP(min) BA NOP T9 T10 tWR D0 D1 D2 D3 DQS DQ tWR BA |
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