T89C51AC2-RLSI-M datasheet(95/117 Pages) ATMEL

95 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt

Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts

at the same time.

Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a

bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each

combination.

Table 22. Priority Level Bit Values

A low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. A

high-priority interrupt cannot be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of the higher priority

level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling

sequence determines which request is serviced. Thus within each priority level there is a second priority structure

determined by the polling sequence, see Table 23.

Table 23. Interrupt priority Within level

IPH.x

IPL.x

Interrupt Level Priority

0 (Lowest)

011

102

3 (Highest)

Interrupt Name

Interrupt Address Vector

Priority Number

external interrupt (INT0)

0003h

Timer0 (TF0)

000Bh

external interrupt (INT1)

0013h

Timer1 (TF1)

001Bh

PCA (CF or CCFn)

0033h

UART (RI or TI)

0023h

Timer2 (TF2)

002Bh

---

ADC (ADCI)

0043h

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