C167CS-4RM datasheet(19/517 Pages) INFINEON

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C167CS

Derivatives

Architectural Overview

User’s Manual

2-2

V2.0, 2000-07

2.1

Basic CPU Concepts and Optimizations

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic

and logic unit (ALU) and dedicated SFRs. Additional hardware is provided for a separate

multiply and divide unit, a bit-mask generator and a barrel shifter.

Figure 2-2

CPU Block Diagram

To meet the demand for greater performance and flexibility, a number of areas has been

optimized in the processor core. Functional blocks in the CPU core are controlled by

signals from the instruction decode logic. These are summarized below, and described

in detail in the following sections:

1) High Instruction Bandwidth/Fast Execution

2) High Function 8-bit and 16-bit Arithmetic and Logic Unit

3) Extended Bit Processing and Peripheral Control

4) High Performance Branch-, Call-, and Loop Processing

5) Consistent and Optimized Instruction Formats

6) Programmable Multiple Priority Interrupt Structure

MCB02147

CPU

STKOV

STKUN

Instr. Reg.

Instr. Ptr.

Exec. Unit

4-Stage

Pipeline

MDH

MDL

PSW

SYSCON

Context Ptr.

Mul/Div-HW

R15

General

Purpose

Registers

Bit-Mask Gen

Barrel - Shifter

ALU

(16-bit)

Data Page Ptr.

Code Seg. Ptr.

Internal

RAM

R15

ROM

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

ADDRSEL 4

ADDRSEL 3

ADDRSEL 2

ADDRSEL 1

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