T84C5112-RKFCL datasheet(62/97 Pages) ATMEL

62 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

14.7. ADC Standby Mode

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register.

In this mode the power dissipation is about 1uW.

14.8. Voltage referencee

The voltage reference can be either internal or external.

As input, the Vref pin is used to enter the voltage reference for the A/D conversion.

When the voltage reference is active, the Vref pin is an output. This voltage can be used for the A/D and for any

other application requiring a voltage independant from the power supply. Voltage typical value is 2.4 volt and the

load must greater than 18 kOms.

14.9. IT ADC management

An interrupt end-of-conversion will occurs when the bit ADEOC is actived and the bit EADC is set. For re-arming

the interrupt the bit ADEOC must be cleared by software.

Figure 31. ADC interrupt structure

14.10. Registers

Table 35. ADCON Register

ADCON (S:F3h)

ADC Control Register

QUIETM

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit Number Bit Mnemonic

Description

QUIETM

Pseudo Idle mode (best precision)

Set to put in quiet mode during conversion.

Cleared by hardware after completion of the conversion.

PSIDLE

Pseudo Idle mode (good precision)

Set to put in idle mode during conversion.

Cleared by hardware after completion of the conversion.

ADEOC

ADCON.2

EADC

IE1.1

ADCI

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