T84C5112-RKFCL datasheet(17/97 Pages) ATMEL

17 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

In Power-Down mode, the PFD is automatically disabled; this avoids extra consumption and allows VDD reduction

to VRET.

Note:

1. The internal reset is not propagated on the RST pin.

2 See AC/DC section for the speciﬁcations of Vrst.

Caution:

When VDD is reduced to VRET in Power-Down mode the VDD voltage is not accuratly monitored. In this case, RAM content may be damage if VDD

goes below VRET and circuit behavior is unpredictable unless an external reset is applied. The POF bit can be used to verify if memory contains valid

data.

Figure 4. Power Fail Reset timing diagram

7.5. Power-Off Flag

When the power is turned off or fails, the data retention is not guaranteed. A Power-Off Flag (POF, see 7.6.1. )

allows to detect this condition. POF is set by hardware during a reset which follows a power-up or a power-fail.

This is a cold reset. A warm reset is an external or a watchdog reset without power failure, hence which preserves

the internal memory content and POF. To use POF, test and clear this bit just after reset. Then it will be set only

after a cold reset.

Notes: When power supply monitoring is disabled (RSTD= 1 or in Power-Down mode), POF information is not delivered with the same

accuracy. It is recommended to clear and not to take in account the POF value after exit from a power down mode with VDD reduction.

Notes: The POF flag is set only if Vcc is lower below the memory data retention voltage. Hence, the PFD may detect a power fail while the

POF bit is still valid.

24 Ck

RSTVPP

POR

PFD

RST

24 Ck

<60ns

>60ns

VRST+

VRST

VRET

T84C5112-RKFCL 데이터시트(PDF) 17 Page - ATMEL Corporation