Handshake Solutions
HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Page 46 of 132
© Philips Electronics N.V. 2005
S1STA
SIO1 status register
addr = D9H
reset value = F8H
bits
7
6
5
4
3
2
1
0
status
0
0
0
bit
symbol
Function
S1STA.7
S1STA.6
S1STA.5
S1STA.4
S1STA.3
Status code. The status is valid as long as SI is set. When no relevant
status is available, S1STA contains the value F8H.
S1STA.2
S1STA.1
S1STA.0
Always 0.
5.5.3.
Interrupts
The HT-I2C can generate only one interrupt. If the bit SI in the SFR S1CON is set, an interrupt is re-
quested on line int_req_i[5]. SI is set by hardware but has to be cleared by software, for instance
in the interrupt service routine.
5.5.4.
Operation
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the bus are:
•
Bidirectional data transfer between masters and slaves
•
Multimaster bus (no central master)
•
Arbitration between simultaneously transmitting masters without corruption of serial data on the
bus
•
Serial clock synchronization allows devices with different bit rates to communicate via one serial
bus
•
Serial clock synchronization can be used as a handshake mechanism to suspend and resume
serial transfer
•
The I2C bus may be used for test and diagnostic purposes
The HT-I2C logic (here also named SIO1) provides a serial interface that meets the I2C bus specifica-
tion and supports all transfer modes (other than the low-speed mode) from and to the I2C bus. The
HT-I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status
register (S1STA) reflects the status of HT-I2C and the I2C bus.
The CPU interfaces to the I2C logic via the following four special function registers: S1CON (SIO1 con-
trol register), S1STA (SIO1 status register), S1DAT (SIO1 data register), and S1ADR (SIO1 slave address
register). The SIO1 logic interfaces to the external I2C bus via two port 1 pins: SCL (serial clock line)
and SDA (serial data line).
A typical I2C bus configuration is shown in [Figure 14]. [Figure 15] shows how a data transfer is ac-
complished on the bus. Depending on the state of the direction bit (R/W), two types of data transfers
are possible on the I2C bus:
1.
Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an ac-
knowledge bit after each received byte.
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
