STLC5048 datasheet(43/45 Pages) STMICROELECTRONICS

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STLC5048

APPENDIX C

Power Up Sequence

The DSP after an HW (M1=0) or SW reset (CONF[7]=1) or a Power-on reset (POR) has to perform the INIT

proram. To do it at least one channel must be set in active mode.

After that, (2 FS are required), the INIT bit in the CTRLACK register is set to 1 and the RAM can be written and

read. It must be noted that to program the device the MCLK and FS signals must be applied to the device.

Following, the correct sequence that must be used in order to program the device.

Power on sequence

wait 5 FS signals for PLL locking

CONF=BF

Sw Reset enabled after reset

write CONF=3F

Sw Reset disabled

write CONF=30

All Channel Active

wait 2 FS signals

read CTRLACK=03

Check INIT bit =1

Before to start the coefficent download, one or more channels must be selected using the COMEN register. The

download can be done keeping the device in Active mode (at least one channel active) or in Power Down mode

(all channels in Power Down). If the second choice is selected, the PDR bit in the COMEN register must be set

to 0 (internal RAM active also in Power Down mode).

STLC5048 데이터시트(PDF) 43 Page - STMicroelectronics