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STLC5432 데이터시트(PDF) 17 Page - STMicroelectronics

부품명 STLC5432
상세설명  2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
PDF  46 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STLC5432 데이터시트(HTML) 17 Page - STMicroelectronics

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9.12 PCR1: PRS Counter Register 1
70
1
P6
P5
P4P3
P2P1P0
After Reset = 80H
P0/6
7 less significant bits of the Pseudo Random
Counter Register.
9.13 PCR2: PRS Counter Register 2
70
1
P13
P12
P11
P10
P9
P8
P7
After Reset = 80H
P7/13 7 most significant bits of the PseudoRandom
Counter Register.
PCR1 and PCR2 are two registers associated to
Pseudo Random Sequence Counter.
When the Pseudo Random Sequence Analyser is
validated, the counter indicates the number of er-
roneus bits received after the synchronisation of
the Pseudo Random Sequence.
9.14 ERTR: Error Rate Threshold Register
70
1
IT2
IT1
IT0
VT3
VT2
VT1
VT0
After Reset = B8H
VT 0/3 Error Rate Validation Threshold of WER.
VT0/3 bits give the threshold of activating
the indication of Alarm for erroneous Frame
Alignment words.
WER is set to ”1” only if the fault condition
is confirmed within the following 2 seconds.
VT3
VT2
VT1
VT0
Number of erroneous
Frame Alignement
words received during
2 seconds
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
16
18
20
22
24
26
28
30
32
36
40
44
48
52
56
60
IT 0/2
Error Rate Inhibition Threshold of WER
IT 0/2 bits give the threshold of deactivating
the indication of Alarm. Per default, WER is
set at ”0” when 12 or less erroneous
Frame Alignment Words are detected.
The Alarm deactivation requires the confir-
mation of the condition for the following 2 sec.
IT2
IT1
IT0
Number of erroneous
Frame Alignment words
received during 2 seconds
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
9
10
12
14
16
20
24
NB: If the threshold value of deactivating the indi-
cation of Alarm is superior to threshold value of
activating the indication of Alarm, then the value
of deactivating is irrelevant.
9.15 TS0RR: Time Slot Zero Received Register
70
1
0
0
Sa4R Sa5R Sa6R Sa7R Sa8R
After Reset 80H
Sa4R to Sa8R Bits 4 to 8 of the odd Time Slot
Zero (Sa4 to Sa8) received from the
line. During reframe time, these bit
are at ”1”. Sa4R to Sa8R fix the
contentof TS0RR in accordancewith
CR8 Register and bit POLSa (CR6
register)
9.16 Sa6RR: Sa6 Bits Receive Register
70
1
0
AR
Sa5R Sa61R Sa62R Sa63R Sa64R
After Reset = 9FH
Sa61R to Sa64R
These four bits are received from Sa6 subchan-
nel.
When a new word constituted by these four bits is
detected in accordance with SaT (CR6 Regis-
ters), a Sa6R interrupt is generated (a new word
can occur each millisecond).
Sa5R. Thisbit is thesameasSa5R inTS0RR register.
AR
A bit received. It’s the same bit than the AR
bit of ALR register (see 9.2).
STLC5432
17/46



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