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STLC5432 데이터시트(PDF) 25 Page - STMicroelectronics

부품명 STLC5432
상세설명  2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
PDF  46 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5432 데이터시트(HTML) 25 Page - STMicroelectronics

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9.33 TCR2: Test Configuration Register 2
70
1
SAV
ATS5 ATS4 ATS3 ATS2 ATS1 ATS0
After Reset = 80H
ATS0 to ATS5 Time Slot associated to Analyzer.
These 6 bits indicate Time Slot(s)
selected to receive the Pseudo
Random Binary
Sequence (PRBS). The internal analyzer
checks the sequence.
SAV
Sequence Analyzer Validated.
When SAV is at ”1”, the analyzer is
validated and the counter ECR1-ECR2
(14 bits) is associated to analyzer. The
length of PRBS is in accordance with NR
bit. After the sequence is recovered by the
analyzer. PRSR is set at ”1”
(Complementry Alarm
Register); the associated counter indicates
the number of faults received.
ATS5
ATS4
ATS3
ATS2
GTS1
GTS0
Time Slot(s) selected to receive PRBS
0
0
0
0
0
0
All the Time Slots except TS0
0
X
X
X
X
1
All the Time Slots including TS0
1
0
0
0
0
0
Not use
1
000
01
TS1
1
000
10
TS2
↓↓
↓↓
↓
↓
↓
1
1
1
1
1
0
TS30
1
1
1
1
1
1
TS31
9.32 TCR1: Test Configuration Register 1
70
1
SGV GTS5 GTS4 GTS3 GTS2 GTS1 GTS0
After Reset = 80H
GTS0 to GTS5 Time Slot associated to generator.
These 6 bits indicate Time Slot(s)
selected to transmit the Pseudo
Random Binary
Sequence(PRBS) provided by the internal
generator (see Table).
SGV
Sequence Generator Validated.
When SGV is at ”1”, the generator provides
Pseudo Random Binary Sequence in
accordance with NX bit. When SGV is at 0,
the generator is not validated.
GTS5
GTS4
GTS3
GTS2
GTS1
GTS0
Time Slot(s) selected to transmit
PRBS
000000
All the Time Slots except TS0
0
X
X
X
X
1
All the Time Slots including TS0
100000
Not use
100001
TS1
100010
TS2
↓
↓↓↓
↓↓
↓
111110
TS30
111111
TS31
STLC5432
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