STLC5444 datasheet(3/17 Pages) STMICROELECTRONICS

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PIN DESCRIPTION

Name

PLCC

DIP

Function

Bit 1 of the tri state I/O data bus

2,4,8,10,

13,14,

16,18,

20,23,

25,26,

28,34,

37,38,44

7,9

No connection

Bit 0 of the tri state I/O data bus

INT

Active low interrupt output for the

µP (open drain)

VBB

6,7

15,17

22,29,

39,40

8,12

Battery supply line (negative battery‘s terminal)

BGND

Battery ground line

VCC

+5V supply line

ILIM

Current limit programming

Output of the power switch controller 0

Output of the power switch controller 1

Output of the power switch controller 2

RSRVD

–

Reserved pin: it must be left floating

Output of the power switch controller 3

RESET

Active high reset input

Active low read input

Active low chip select input

Active low write input

ALE

Active high address latch enable

DGND

Digital ground

Address bit for R/W operations on the data bus

Bit 3 of the I/O tri state data bus

Bit 2 of the I/O tri state data bus

FUNCTIONAL DESCRIPTION

ADDRESS LINE (Input)

A0 selects source and destination locations for

read and write operations on the data bus. A0

must be valid on the falling edge of ALE or during

RD and WR if ALE is tied High.

ALE - Address Latch Enable (Input; Active

High)

ALE is an input control pulse used to strobe the

address on the A0 line into the address latch.

This signal is active High to admit the input ad-

dress. The address is latched on the High-Low

transition of ALE. While ALE is High, the address

latch is transparent. For an unmultiplexed micro-

processor bus, ALE must be tied High.

BGND - Ground Battery

CS - Chip Select (Input; Active Low)

CS must be Low to enable the read or write op-

erations of the device. Data transfer occurs over

the D3-D0 lines.

D3-D0 - DATA BUS (Input/Output; Three-State)

The four bidirectional data bus lines are to ex-

change information with a microprocessor. D0 is

the least significant bit and D3 is the most signifi-

cant bit. A High on the data bus corresponds to a

logical 1. These lines act as input when WR and

CS are active and as output when RD and CS are

active. When CS is inactive, the D3-D0 pins are

placed in a high-impedance state.

STLC5444

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