The LER is used to enable or disable the individ-

ual line drivers. The line drivers will only become

active if the corresponding bit in the TOR is inac-

tive. The LER is a read/write register.

The MPI is the interface containing the following

pins :

D3-D0

Bidirectional

Data Bus

A0

Input

Address Line

ALE

Input

Address Latch Enable

RD

Input

Read Enable

WR

Input

Write Enable

CS

Input

Chip Select

INT

Output

COD Interrupt

RESET

Input

Reset pin

The 4-bit bidirectional data bus (D3-D0) is used to

communicate with the registers. Access to the

registers is controlled by CS, RD, WR, ALE, and

A0 as shown below. A read or write cycle must be

preceded by a valid A0. A0 is latched internally in

a transparent latch by ALE. The selection of the

status group or the LER is determined by the con-

tent of the IAR.

The truth table for the MPI control is shown below

:

CS

RD

WR

A0

0

1

0

0

Write IAR (T bit is read only)

0

0

1

0

Read IAR and T bit

0

1

0

1

Write LER

0

0

1

1

Read status groups or LER

1

X

X

X

No access

Indirect Address Register (IAR) and T/I Bit

The IAR is 3 bits wide and accessible through the

data port, D2-D0. The content of the Indirect Ad-

dress Register (IAR2-IARO) determines the se-

lection of the status groups or the LER. The ther-

mal overload bit T/I is read and written at the

same time as IAR and occupies D3.

This register has the following format :

Bit

Symbol

0

1

2

3

IARO

IAR1

IAR2

T/I

Bit 0 of the IAR

Bit 1 of the IAR

Bit 2 of the IAR

T bit: (Read only)

Logical 0: temperature normal (default value)

Logical 1: temperature above 160

°C (all drivers shut off)

I bit

: (write only)

Logical 0: INT pin disabled

Logical 1: COD interrupts enabled via INT pin‘

IAR2-IAR0 address the status groups and the LER as shown below:

IAR2

IAR1

IAR0

Select

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

LVD

OLD

COD

LEC

RESERVED

RESERVED

LER

TOR

STLC5444

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