LER :

Bit

Logical 1

Logical 0 (default value)

0

1

2

3

O0 on

O1 on

O2 on

O3 on

O0 off

O1 off

O2 off

O3 off

The Line Enable Register (LER) is used to enable or disable the individual output line drivers. The output

line will only become active if the corresponding bit in the TOR is set to a logical 1. The LER can be writ-

ten directly and read indirectly.

°Cto 70°C)

Parameter

Value

Voltage from Digital Input to DGND

-0.4V to +7V

-130V to +0.4V

100ns Pulse voltage from Si to DGND (See Notes)

-130V to +2V

Voltage from BGND to DGND

+0.5V, -3V

Storage Temperature

T = -60

°C to +150°C

Note : Si stands for O0, O1, O2 or O3 outputs.

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol1

Min.

Max.

Units

(*) Ambient Temperature

for standard type

for ext. temperature type

0

-40

70

85

°C

°C

Supply Voltage

DGND

BGND

4.75

-115

0

-3

5.25

-38

0

+0.5

V

V

V

V

Programmed Limiting Current

120

mA

(*): Specifications in this data sheet are guaranteed by testing from 0

°C to +70°C. For extended temperature range types, performance from

–40

°C to +85°C is guaranteed by characterization and periodic sampling of production units.

APPLICATION HINT

In the Absolute Maximum Ratings table it is speci-

should never exceed by more than 0.4V the volt-

age applied on the Ground pin.

As long as the external circuitry assures compli-

ance with the above, no more considerations are

needed.

In some cases however it may be not possible to

exclude that conditions may occur (hot insertion,

power supply transients, etc.) where the negative

supply has a transient overshoot above ground

voltage. Then a protection circuitry that clamps

such overshoot can add to the equipment reliabil-

ity. Such protection can be designed taking into

considerations that typically the devices behave

as follows:

pins are normally biased, the chip generates

on it an open circuit voltage of +420mV.

- if all the other pins are normally biased and

10mA flows into it. At the same time from +5V

a current of 4mA is absorbed (this low current

from +5V simply means that no parasitic

latch-ups are triggered inside the chip). No

deterioration of the device occurs.

- if all the other pins are normally biased, and

period, no deterioration of the device occurs.

Transient period can be considered any time

interval that lasts for less than 10

µs and is not

repeated more than 5000 times during the

device lifetime.

ORDERING TYPES:

STLC5444B1, PDIP24 package: 0 to 70

°C Temperature range.

STLC5444FN, PLCC44 package: 0 to 70

°C Temperaturerange.

STLC5444B1-X, PDIP24 package: -40 to 85

°C Temperature range.

STLC5444FN-X, PLCC44 package: -40 to 85

°C Temperature range.

STLC5444

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