STLC5460 datasheet(20/54 Pages) STMICROELECTRONICS

20 / 54 page

FIRST CASE CM = 1: ACCESS TO COMMAND MEMORY

CR5

CR4

CR3

CR2

CR1

CR0

R/W

CH1

CH0

SS1

SS0

DS1

DS0

After Reset 00 (H)

R/W

Read/Write

R/W = 0 (Write). The eight bits of Source Register and the six lower bits of this

Command Register are loaded into the Command Memory (14 bits). The Address bits

are given by the Destination Register (8 bits). Write cycle starts when Destination

R/W = 1 (Read).

The 14 bits of Command memory addressed by the Destination Register are loaded

respectively into Command Register (6 bits) and Source Register (8 bits). Read cycle

starts when Destination Register is loaded by the micro-processor.

CH0/1

Channel Data Rate

CH1

CH0

Description

The output is at high impedance during the time slot selected

16kb/s subchannel is selected

32kb/s subchannel is selected

64kb/s channel is selected

During the time slot selected, the output is at high impedance for the subchannels not selected.

SS 0/1

Source Subchannel selected.

Data Rate

SS1

SS0

Source channel

16kb/s

Bits 6-7

Bits 4-5

Bits 2-3

Bits 0-1

32kb/s

Bits 4 to 5

Bits 0 to 3

Bit 7 is trasmitted first.

DS 0/1

Destination Subchannel selected.

Data Rate

SS1

SS0

Source channel

16kb/s

Bits 6-7

Bits 4-5

Bits 2-3

Bits 0-1

32kb/s

Bits 4 to 5

Bits 0 to 3

Bit 7 is trasmitted first.

STLC5460

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