STLC5465B datasheet(45/101 Pages) STMICROELECTRONICS

45 / 101 page

V - CLOCK TIMING

V.1 - Synchronization Signals delivered by the system

For one of three different input synchronizations which is programmed, FSCG and FSCV* signals

delivered by the

Multi-HDLC are in accordance with the figure hereafter.

t5h

t5l

Bit4

Bit5

Bit0

Bit1

Bit6

Bit7

Bit3

Time S lot 31

Time S lot 0

t4 CGI

CLOCK B

CLOCK A

1) S y Mode

Fra me A (or B)

2) GCI Mod e

Fra me A (or B)

3) V* Mod e

Fra me A (or B)

DIN 0/8, E CHO

DO UT 0/7, C B

if FS = F S CG

TDM0/7

FS CG de livere d

by the circuit

FS CV* delivere d

by the circuit

The four Multiplex Configura tion Regis te rs a re a t ze ro (no de lay).

Figure 34 : Clocks received and delivered by the

Multi-HDLC

Symbol

Parameter

Min.

Typ.

Max.

Unit

Clock Period if 4096kHz (3072)

Clock Period if 8192kHz (6144)

239 (320)

120 (158)

244 (325)

122 (162)

249 (330)

125 (165)

Delay between Clock A and Clock B

- 60

+60

Set up time Frame A (or B)/CLOCK A (or B)

t1-10

t4GCI

Hold time Frame A (or B)/CLOCK A (or B)

t1-10

125000 - (t1 - 10)

Clock ratio t5h/t5l

100

125

Duration of FSCG

488

STLC5465B

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