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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST6208LD1/OTP 데이터시트(PDF) 72 Page - STMicroelectronics |
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ST6208LD1/OTP 데이터시트(HTML) 72 Page - STMicroelectronics |
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72 / 104 page  ST6208C/ST6209C/ST6210C/ST6220C 72/104 10.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 10.5.1 General Timings 10.5.2 External Clock Source Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. ∆t c(INST) is the number of tCPU cycles needed to finish the current instruction execution. Figure 49. Typical Application with an External Clock Source Symbol Parameter Conditions Min Typ 1) Max Unit tc(INST) Instruction cycle time 24 5 tCPU fCPU=8 MHz 3.25 6.5 8.125 µs tv(IT) Interrupt reaction time 2) tv(IT) = ∆tc(INST) + 6 611 tCPU fCPU=8 MHz 9.75 17.875 µs Symbol Parameter Conditions Min Typ Max Unit VOSCINH OSCIN input pin high level voltage See Figure 49 0.7xVDD VDD V VOSCINL OSCIN input pin low level voltage VSS 0.3xVDD IL OSCx Input leakage current VSS≤VIN≤VDD ± 2 µA OSCIN OSCOUT fOSC EXTERNAL ST62XX CLOCK SOURCE VOSCINL VOSCINH IL 90% 10% Not connected 1 |
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