Timing diagrams

STP24DP05

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Timing diagrams

Figure 8.

Timing diagram

Note:

The latches circuit holds data when the LE terminal is low.

1

When LE\DML terminal is at high level, latch circuit hold the data it passes from the input to

the output.

2

When either OE-R\DM, OE-G, OE-B terminals are at low level, output terminals R\G\B1 to

R\G\B8 respond to the data, either ON or OFF.

3

When either OE-R\DM, OE-G, OE-B terminals are at high level, it switches off all the data on

the output terminal R\G\B1 to R\G\B8.