PM6681ATR datasheet(37/47 Pages) STMICROELECTRONICS

부품명	PM6681ATR

상세설명	Dual synchronous step-down controller with adjustable LDO

PDF	47 Pages

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37 / 47 page

PM6681A

Design guidelines

37/47

where

∆I

L is the inductor current ripple and VRIPPLE is the overall ripple of the T node

voltage. It should be chosen higher than approximately 30 mV.

The new closed loop gain depends on CINT. In order to ensure stability it must be verified

that:

Equation 30

Where:

Equation 31

where RTOT is the sum of the ESR of the output capacitor Rout and the equivalent ESR

given by the virtual ESR network RESR.

Moreover CINT must meet the following condition:

Equation 32

Where k is a free design parameter greater than 3 and determines the minimum integrator

capacitor value CINT:

Equation 33

C must be selected as shown:

Equation 34

R must be chosen in order to have enough ripple voltage on integrator input:

Equation 35

R1 can be selected as follows:

OUT

INT

TOT

out

TOT

out

OUT

INT

⎟

⎠

⎞

⎜

⎝

⎛

−

INT

ESR ×

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