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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA335BWS 데이터시트(PDF) 63 Page - STMicroelectronics |
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STA335BWS 데이터시트(HTML) 63 Page - STMicroelectronics |
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63 / 68 page  STA335BWS Application 63/68 Figure 18. PLL application scheme 7.3 Typical output configuration Here after the typical output configuration used for BTL stereo mode. Please refer to the application note for all the other possible output configuration recommended schematics. Figure 19. Output configuration for stereo BTL mode 100pF FILTER_PLL 680pF 4.7nF 2K2 100pF FILTER_PLL 680pF 4.7nF 2K2 BEAD PLL_GND GND_DIG 100pF FILTER_PLL 680pF 4.7nF 2K2 100pF FILTER_PLL 680pF 4.7nF 2K2 BEAD BEAD PLL_GND GND_DIG 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 LEFT 100nF 6.2 OUT1A OUT1B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 RIGHT 100nF 6.2 OUT2A OUT2B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 LEFT 100nF 6.2 OUT1A OUT1B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 LEFT 100nF 6.2 OUT1A OUT1B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 RIGHT 100nF 6.2 OUT2A OUT2B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 RIGHT 100nF 6.2 OUT2A OUT2B 6.2 |
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