ADA4857-2YCPZ-R2 datasheet(16/20 Pages) AD

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ADA4857-1/ADA4857-2

Rev. 0 | Page 16 of 20

APPLICATIONS INFORMATION

PD PIN OPERATION

The PD pin is used to power down the chip, which reduces the

quiescent current and the overall power consumption. It is low

enabled which means that the chip is on with full power when

the PD pin input voltage is low (see Table 8). Note that PD

does not put the output in a high-Z state, which means that

the ADA4857 should not be used as a multiplexer.

Table 8. PD Operation Table Guide

PD Pin Voltage

Supply Voltage

Chip

≤+0.8 V

±5 V

Enabled

≥+3 V

±5 V

Powered down

≤−1.7 V

±2.5 V

Enabled

≥+0.5 V

±2.5 V

Powered down

≤+0.8 V

+5 V

Enabled

≥+3 V

+5 V

Powered down

No connect

All

Enabled

CAPACITIVE LOAD CONSIDERATIONS

When driving a capacitive load, RSNUB is used to reduce the

peaking (see

). An optimum resistor value of 40 Ω is

found to maintain the peaking within 1 dB for any capacitive

load up to 40 pF.

Figure 45

RECOMMENDED VALUES FOR VARIOUS GAINS

Table 9 provides a useful reference for determining various

gains and associated performance. Resistors RF and RG are

kept low to minimize their contribution to the overall noise

performance of the amplifier.

Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; VS = ±5 V, TA = 25°C, RL = 1 kΩ, RT = 49.9 Ω

Gain

RF (Ω)

RG (Ω)

−3 dB SS BW (MHz),

VOUT = 200 mV p-p

Slew Rate (V/μs),

VOUT = 2 V Step

ADA4857 Voltage

Noise (nV/√Hz), RTO

Total System

Noise (nV/√Hz), RTO

N/A

850

2350

4.4

4.49

499

360

1680

8.8

9.89

499

124

516

22.11

23.49

+10

499

56.2

213

43.47

45.31

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