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P60NS04Z 데이터시트(PDF) 1 Page - STMicroelectronics |
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P60NS04Z 데이터시트(HTML) 1 Page - STMicroelectronics |
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1 / 8 page ![]() STP60NS04Z N - CHANNEL CLAMPED 10m Ω - 60A - TO-220 FULLY PROTECTED MESH OVERLAY ™ MOSFET PRELIMINARY DATA s TYPICAL RDS(on) = 0.010 Ω s 100% AVALANCHE TESTED s LOW CAPACITANCE AND GATE CHARGE s 175 oC MAXIMUM JUNCTION TEMPERATURE DESCRIPTION This fully clamped Mosfet is produced by using the latest advanced Company’s Mesh Overlay process which is based on a novel strip layout. The inherent benefits of the new technology coupled with the extra clamping capabilities make this product particularly suitable for the harshest operation conditions such as those encountered in the automotive environment. Any other application requiring extra ruggedness is also recommended. APPLICATIONS s ABS, SOLENOID DRIVERS s MOTOR CONTROL s DC-DC CONVERTERS ® INTERNAL SCHEMATIC DIAGRAM December 1999 1 2 3 TO-220 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Un it VDS Drain-source Voltage (VGS = 0) CLAMPED V VDG Drain- gate Voltage CLAMPED V VGS G ate-source Volt age CLAMPED V ID Drain Current (continuous) at Tc =25 oC60 A ID Drain Current (continuous) at Tc = 100 oC42 A IDG Drain Gate Current (continuous) ± 50 mA IGS G ate Source Current (cont inuous) ± 50 mA IDM ( •) Drain Current (pulsed) 240 A Ptot T otal Dissipation at Tc =25 oC 140 W Derating Factor 0.93 W / o C VESD (G-S) Gate-Source ESD (HBM - C= 100pF, R=1.5 k Ω)2 kV VESD(G-D) G ate-Drain ESD (HBM - C= 100pF, R=1.5 k Ω)4 kV VESD(D-S) Drain-Source ESD (HBM - C= 100pF, R=1.5 k Ω)4 kV Tstg Storage Temperature -65 to 175 o C Tj Max. Operating Junction Temperature -40 to 175 o C ( •) Pulse width limited by safe operating area ( 1)ISD ≤60 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS,Tj ≤ TJMAX TYPE VDSS RDS(on) ID STP60NS04Z CLAMPED <0.015 Ω 60 A 1/8 |
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