M41ST87Y_08 datasheet(24/48 Pages) STMICROELECTRONICS

24 / 48 page

Operating modes

M41ST87Y, M41ST87W

24/48

Table 5.

Tamper detect timing

Figure 19.

RAM clear hardware hookup

Most inverting charge pumps drive OUT to ground when device shut down is enabled (SHDN = logic low). Therefore, an n-

channel enhancement mode MOSFET should be used to isolate the OUT pin from the VOUT of the M41ST87.

In order to avoid turning on an on-chip parasitic diode when driving VOUT negative, a p-channel enhancement mode

MOSFET should be used to isolate the VOUT pin from the negative voltage generated by the inverting charge pump.

2.7

Tamper detection operation

The tamper pins are triggered based on the state of an external switch. Two switch mode

options are available, “normally open” or “normally closed,” based on the setting of the

Symbol

Parameter

CLRPW

Min

Typ

Max

Unit

tCLRD

(1)

With input capacitance = 70 pF and resistance = 50

Ω.

Tamper RAM clear ext delay

1.0(2)

If the OF bit is set, tCLRD(min) = 0.5 ms.

1.5

2.0

tCLR

Tamper clear timing

AI07804

VCC

PFO1

SCL

M41ST87Y/W

WDI

RSTIN1

RSTIN2

PFI1

PFI2

VSS

VBAT

F32k

IRQ/OUT

SQW/FT

RST

VOUT

ECON

SDA

CAP+ CAP–

Inverting

Charge

Pump

SHDN

OUT

TP1IN

TPCLR

TP2IN

Pushbutton

Reset

PFO2

Low-Power

SRAM

VCC

Negative Output

(–1 x VIN)

To RST

To LED Display

(2)

(1)

To NMI

To INT

To 32kHz

Inhibit

Regulator

VCC

VIN

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