| 전자부품 데이터시트 검색엔진 |
|
MSC7116 데이터시트(PDF) 30 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MSC7116 데이터시트(HTML) 30 Page - Freescale Semiconductor, Inc |
|
30 / 60 page ![]() MSC7116 Data Sheet, Rev. 13 Electrical Characteristics Freescale Semiconductor 30 2.5.6.2 Transmit Signal Timing 2.5.6.3 Asynchronous Input Signal Timing Table 22. Transmit Signal Timing No. Characteristics Min Max Unit 800 Transmit clock period: • MII: TXCLK • RMII: REFCLK 40 20 — — ns ns 801 Transmit clock pulse width high—as a percent of clock period • MII: RXCLK • RMII: REFCLK 35 14 7 65 — — % ns ns 802 Transmit clock pulse width low—as a percent of clock period: • MII: RXCLK • RMII: REFCLK 35 14 7 65 — — % ns ns 805 Transmit clock to TXDn, TX_EN, TX_ER invalid 4 — ns 806 Transmit clock to TXDn, TX_EN, TX_ER valid — 14 ns Figure 11. Ethernet Receive Signal Timing Table 23. Asynchronous Input Signal Timing No. Characteristics Min Max Unit 807 • MII: CRS and COL minimum pulse width (1.5 × TXCLK period) • RMII: CRS_DV minimum pulse width (1.5 x REFCLK period) 60 30 — — ns ns Figure 12. Asynchronous Input Signal Timing Valid Transmit TX_EN TXDn TX_ER 805 806 clock 800 801 802 CRS COL 807 CRS_DV |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |