MSC7116 datasheet(55/60 Pages) FREESCALE

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Hardware Design Considerations

MSC7116 Data Sheet, Rev. 13

Freescale Semiconductor

3.5.1

VREF and VTT Design Constraints

VTT and VREF are isolated power supplies at the same voltage, with VTT as a high current power source. This section outlines

the voltage supply design needs and goals:

•

Minimize the noise on both rails.

•VTT must track variation in the VREF DC offsets. Although they are isolated supplies, one possible solution is to use a

single IC to generate both signals.

•

Both references should have minimal drift over temperature and source supply.

•

It is important to minimize the noise from coupling onto VREF as follows:

— Isolate VREF and shield it with a ground trace.

— Use 15–20 mm track.

— Use 20–30 mm clearance between other traces for isolating.

— Use the outer layer route when possible.

— Use distributed decoupling to localize transient currents and return path and decouple with an inductance less than

3 nH.

•

Max source/sink transient currents of up to 1.8 A for a 32-bit data bus.

•

Use a wide island trace on the outer layer:

— Place the island at the end of the bus.

— Decouple both ends of the bus.

— Use distributed decoupling across the island.

— Place SSTL termination resistors inside the VTT island and ensure a good, solid connection.

•

Place the VTT regulator as closely as possible to the termination island.

— Reduce inductance and return path.

— Tie current sense pin at the midpoint of the island.

3.5.2

Decoupling

The DDR decoupling considerations are as follows:

•

DDR memory requires significantly more burst current than previous SDRAMs.

•

In the worst case, up to 64 drivers may be switching states.

•

Pay special attention and decouple discrete ICs per manufacturer guidelines.

•

Leverage VTT island topology to minimize the number of capacitors required to supply the burst current needs of the

termination rail.

•

See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel

(http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf).

Figure 37. SSTL Power Value

Driver

Receiver

VREF

VDDQ

VSS

VTT

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