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MSC8112 데이터시트(PDF) 32 Page - Freescale Semiconductor, Inc |
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MSC8112 데이터시트(HTML) 32 Page - Freescale Semiconductor, Inc |
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32 / 44 page ![]() MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 32 2.5.10 Ethernet Timing 2.5.10.1 Management Interface Timing 2.5.10.2 MII Mode Timing Table 24. Ethernet Controller Management Interface Timing No. Characteristics Min Max Unit 801 ETHMDIO to ETHMDC rising edge set-up time 10 — ns 802 ETHMDC rising edge to ETHMDIO hold time 10 — ns Figure 23. MDIO Timing Relationship to MDC Table 25. MII Mode Signal Timing No. Characteristics Min Max Unit 803 ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time 3.5 — ns 804 ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold time 3.5 — ns 805 ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay 1 14.6 ns Figure 24. MII Mode Signal Timing Valid ETHMDC ETHMDIO 802 801 Valid ETHRX_CLK ETHRX_DV ETHRXD[0–3] ETHTX_CLK ETHRX_ER ETHTX_EN ETHTXD[0–3] Valid Valid ETHTX_ER 803 804 805 |
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