HD404612FS datasheet(86/91 Pages) RENESAS

86 / 91 page

HD404618 Series

During Transmit Clock Input

Item

Symbol

Pin(s)

Min

Typ

Max

Test Condition Unit

Notes

Transmit clock

cycle time

Scyc

SCK

1—

—

cyc /tsubcyc 1, 3

Transmit clock

high width

SCKH

SCK

0.5

—

Scyc

Transmit clock

low width

SCKL

SCK

0.5

—

Scyc

Transmit clock

rise time

SCKr

SCK

—

200

Transmit clock

fall time

SCKf

SCK

—

200

Serial output

data delay time

DSO

—

500

Load shown in

figure 54

Serial input data

setup time

SSI

300

—

Serial input data

hold time

HSI

300

—

Transmit clock

completion

detect time

SCKHD

SCK

1—

—

cyc /tsubcyc 1, 2, 3

Notes: 1. See figure 53.

2. The transmit clock completion detect time is the high level period after eight transmit clock

pulses have been input. The serial interrupt request flag is not set if the next transmit clock is

input before the transmit clock completion detect time has passed.

3. The unit t

subcyc applies when the MCU is in subactive mode.

subcyc = 244.14 µs (32.768-kHz crystal oscillator)

TONEC

TONER

R = 100 k

Ω

R = 100 k

Ω

Figure 48 Tone Output Load Circuit

HD404612FS 데이터시트(PDF) 86 Page - Renesas Technology Corp

HD404612FS 데이터시트(HTML) 86 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

데이터시트 다운로드

링크 URL