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M66290AFP 데이터시트(PDF) 14 Page - Renesas Technology Corp

부품명 M66290AFP
상세설명  USB DEVICE CONTROLLER
PDF  54 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M66290AFP 데이터시트(HTML) 14 Page - Renesas Technology Corp

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USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
13
Endpoint5-0 buffer
ready
interrupt enable
Reset
Name
Bit
Name
Bit
If this bit is "1", then the CTRT flag is set when shifted to status stage
in control write transfer.
-
0
0
W/R
Control write
transfer status
stage
WDST
Endpoint5-0 buffer
empty/size error
interrupt enable
-
0
0
W/R
0 : Disable
1 : Enable
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
-
0
0
W/R
Control transfer
sequence error
If this bit is "1", then the CTRT flag is set when control transfer
completed (when the status stage completed normally).
Control transfer
complete
0 : Disable
1 : Enable
If this bit is "1", then the CTRT flag is set when shifted to status stage
in control read transfer.
Control read
transfer status
stage
If this bit is "1", then the DVST flag is set when detected suspend.
Suspend
detect
If this bit is "1", then the DVST flag is set after executed SetConfigration.
Set Configration
execute
If this bit is "1", then the DVST flag is set after executed SetAddress.
Set Address
execute
If this bit is "1", then the DVST flag is set when detected USB reset.
USB reset detect
0 : Disable
1 : Enable
Endpoint5-0 buffer
not ready
interrupt enable
0 : Disable
1 : Enable
1
2
3
4
5
6
7
8
CMPL
RDST
SUSP
SCFG
SADR
URST
INTRE
INTNE
0
9
10
11
12
13
14
SERR
If this bit is "1" then the CTRT flag is set when error
occurred in the sequence of control transfer.
BEMPE
0 : Disable
1 : Enable
Control transfer
interrupt enable
CTRE
0 : Disable
1 : Enable
Device state
interrupt enable
DVSE
SOF interrupt
enable
SOFE
0 : Disable
1 : Enable
Resume interrupt
enable
RSME
-
0
0
W/R
0 : Disable
1 : Enable
VBSE
15
Vbus interrupt
enable
Function
W/R
USB
S/W
H/W
WDST
BEMPE
RDST
INTNE
CTRE
SERR
CMPL
SUSP
SCFG
SADR
URST
INTRE
DVSE
SOFE
RSME
VBSE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D15
D13
D14
(2-1) Interrupt Enable Register 0 (Address : 10h)



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