SH7136 datasheet(28/1160 Pages) RENESAS

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Section 1 Overview

Rev. 2.00 Sep. 10, 2008 Page 2 of 1130

REJ09B0402-0200

Table 1.1

Features of SH7136 and SH7137

Items

Specification

CPU

• Central processing unit with an internal 32-bit RISC (Reduced

Instruction Set Computer) architecture

• Instruction length: 16-bit fixed length for improved code efficiency

• Load-store architecture (basic operations are executed between

registers)

• Sixteen 32-bit general registers

• Five-stage pipeline

• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits)

executed in two to five cycles

• C language-oriented 62 basic instructions

Note:

Some specifications on slot illegal instruction exception handling

in this LSI differ from those of the conventional SH-2. For details,

see section 5.8.4, Notes on Slot Illegal Instruction Exception

Handling.

Operating modes

• Operating modes

 Single chip mode

 Extended ROM enabled mode (SH7137 only)

 Extended ROM disabled mode (SH7137 only)

• Operating states

 Program execution state

 Exception handling state

 Bus release state (SH7137 only)

• Power-down modes

 Sleep mode

 Software standby mode

 Deep software standby mode

 Module standby mode

User break controller

(UBC)

• Addresses, data values, type of access, and data size can all be set as

break conditions

• Supports a sequential break function

• Two break channels

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