SH7136 datasheet(30/1160 Pages) RENESAS

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Section 1 Overview

Rev. 2.00 Sep. 10, 2008 Page 4 of 1130

REJ09B0402-0200

Items

Specification

User debugging

interface (H-UDI)

• Supports the E10A emulator

Clock pulse

generator (CPG)

• Clock mode: Input clock can be selected from external input or crystal

resonator

• Five types of clocks generated

 CPU clock: Maximum 80 MHz

 Bus clock: Maximum 40 MHz

 Peripheral clock: Maximum 40 MHz

 MTU2 clock: Maximum 40 MHz

 MTU2S clock: Maximum 80 MHz

Watchdog timer

(WDT)

• On-chip one-channel watchdog timer

• Interrupt generation is supported

Multi-function timer

pulse unit 2 (MTU2)

• Maximum 16 lines of pulse input/output and 3 lines of pulse input

based on six channels of 16-bit timers

• 21 output compare and input capture registers

• A total of 21 independent comparators

• Selection of eight counter input clocks

• Input capture function

• Pulse output modes

Toggle, PWM, complementary PWM, and reset-synchronized PWM

modes

• Synchronization of multiple counters

• Complementary PWM output mode

 Non-overlapping waveforms output for 6-phase inverter control

 Automatic dead time setting

 0% to 100% PWM duty cycle specifiable

 Output suppression

 A/D conversion delaying function

 Dead time compensation function

 Interrupt skipping at crest or trough

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