R8C datasheet(150/199 Pages) RENESAS

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R8C/10 Group

17. Memory Map

Rev.1.20 Jan 27, 2006

page 140 of 180

REJ09B0019-0120

Table 17.1 Flash Memory Version Performance

17. Flash Memory Version

17.1 Overview

The flash memory version has two modes—CPU rewrite and standard serial I/O—in which its flash

memory can be operated on.

Table 17.1 outlines the performance of flash memory version (see “Table 1.1 Performance” for the items

not listed on Table 17.1).

Item

Flash memory operating mode

Erase block

Method for program

Method for erasure

Program, erase control method

Protect method

Number of commands

Number of program and erasure

ROM code protection

Specification

2 modes (CPU rewrite and standard serial I/O)

See “Figure 17.1. Flash Memory Block Diagram”

In units of byte

Block erase

Program and erase controlled by software command

Blocks 0 and 1 protected by block 0, 1 program enable bit

5 commands

100 times

Standard serial I/O mode is supported.

Table 17.2 Flash Memory Rewrite Modes

Flash memory

CPU rewrite mode

Standard serial I/O mode

rewrite mode

Function

Areas which

User ROM area

can be rewritten

Operation

Single chip mode

Boot mode

mode

ROM

None

Serial programmer

programmer

User ROM area is rewritten by executing

software commands from the CPU.

EW0 mode: Can be rewritten in any area

other than the flash memory

EW1 mode: Can be rewritten in the flash

memory

User ROM area is rewritten by using a

dedicated serial programmer.

Standard serial I/O mode 1

: Clock synchronous serial I/O

Standard serial I/O mode 2

: UART

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