R8C datasheet(151/199 Pages) RENESAS

151 / 199 page

17. Flash Memory Version

R8C/10 Group

Rev.1.20 Jan 27, 2006

page 141 of 180

REJ09B0019-0120

17.2 Memory Map

The ROM in the flash memory version is separated between a user ROM area and a boot ROM area

(reserved area). Figure 17.1 shows the block diagram of flash memory.

The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite

and standard serial I/O modes. Block 1 and Block 0 are enabled for rewrite in CPU rewrite mode by

setting the FMR02 bit in the FMR0 register to “1” (rewrite enabled).

The rewrite program for standard serial I/O mode is stored in the boot ROM area before shipment. The

boot ROM area and the user ROM area share the same address, but have an another memory.

Figure 17.1 Flash Memory Block Diagram

8 Kbytes

0FFFF16

Boot ROM area

(reserved area)(2)

NOTES:

1. When setting the FMR02 bit in the FMR0 register to “1” (rewrite enabled) and the FMR15 bit in the FMR1 register to “0” (rewrite enabled), the Block 0

is rewritable. When setting the FMR16 bit to “0” (rewrite enabled), the Block 1 is rewritable (only for CPU rewrite mode).

2. This area is to store the boot program provided by Renesas Technology.

Block 0 : 8 Kbytes(1)

Block 1 : 8 Kbytes(1)

0FFFF16

0E00016

User ROM area

0C00016

0DFFF16

0E00016

Block 0 : 8 Kbytes(1)

Block 1 : 4 Kbytes(1)

0FFFF16

User ROM area

0D00016

0DFFF16

0E00016

Block 0 : 8 Kbytes(1)

0FFFF16

User ROM area

0E00016

16 Kbytes ROM Product

12 Kbytes ROM Product

8 Kbytes ROM Product

R8C 데이터시트(PDF) 151 Page - Renesas Technology Corp

R8C 데이터시트(HTML) 151 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL