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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7211 데이터시트(PDF) 28 Page - Renesas Technology Corp |
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SH7211 데이터시트(HTML) 28 Page - Renesas Technology Corp |
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28 / 1228 page  Section 1 Overview Rev. 2.00 May. 08, 2008 Page 4 of 1200 REJ09B0344-0200 Items Specification Direct memory access controller (DMAC) • Eight channels; external request available for four of them • Can be activated by on-chip peripheral modules • Burst mode and cycle steal mode • Intermittent mode available (16 and 64 cycles supported) • Transfer information can be automatically reloaded Clock pulse generator (CPG) • Clock mode: Input clock can be selected from external input (EXTAL or CK) or crystal resonator • Input clock can be multiplied by 16 (max.) by the internal PLL circuit • Five types of clocks generated: ⎯ CPU clock: Maximum 160 MHz ⎯ Bus clock: Maximum 40 MHz ⎯ Peripheral clock: Maximum 40 MHz ⎯ Timer clock: Maximum 80 MHz ⎯ AD clock: Maximum 40 MHz Watchdog timer (WDT) • On-chip one-channel watchdog timer • A counter overflow can reset the LSI Power-down modes • Three power-down modes provided to reduce the current consumption in this LSI ⎯ Sleep mode ⎯ Software standby mode ⎯ Module standby mode |
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