M16CSLASH29 datasheet(454/499 Pages) RENESAS

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22. Usage Notes

page 430

22.6 Timers

22.6.1 Timer A

22.6.1.1 Timer A (Timer Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR

(i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to 1 (count

starts).

Always make sure the TAiMR register is modified while the TAiS bit remains 0 (count stops) regard-

less whether after reset or not.

2. While counting is in progress, the counter value can be read out at any time by reading the TAi

is always FFFF16. If the TAi register is read after setting a value in it, but before the counter starts

counting, the read value is the one that has been set in the register.

_____

3. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to 1

_____

(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT

pins go to a high-impedance state.

22.6.1.2 Timer A (Event Counter Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR

(i = 0 to 4) register, the TAi register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the

ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count

starts).

Always make sure bits TAZIE, TA0TGL, and TA0TGH in the TAiMR register, the UDF register, the

ONSF register, and the TRGSR register are modified while the TAiS bit remains 0 (count stops)

regardless whether after reset or not.

2. While counting is in progress, the counter value can be read out at any time by reading the TAi

is always FFFF16 when the timer counter underflows and 000016 when the timer counter overflows.

If the TAi register is read after setting a value in it, but before the counter starts counting, the read

value is the one that has been set in the register.

_____

3. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to 1

_____

(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT

pins go to a high-impedance state.

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