M16CSLASH29 datasheet(483/499 Pages) RENESAS

483 / 499 page

REVISION HISTORY

M16C/29 Hardware Manual

Rev.

Date

Description

Page

Summary

C-1

0.70 Mar/ 29/Y04

“1. Overview” and “1.1. Application” are partly revised.

2, 3

Table 1.2.1 and 1.2.2 are partly revised.

8, 9

Figure 1.5.1 and 1.5.2 are partly revised.

Table 1.6.1 is revised.

Figure 4.8 is partly revised.

Section “5.5 Voltage Detection Circuit” and Figure 5.5.2 are partly revised.

Figure 5.5.3 is partly revised.

Figure 5.5.4 is partly revised.

Section “5.5.1 Voltage Detection Interrupt” and “5.5.1.1.1 Limitations of Stop

Mode” are partly revised.

Figure 7.1 is partly revised.

Figure 7.2 is partly revised.

Figure 7.3 is partly revised.

Figure 7.5 is partly revised.

Figure 7.6 is partly revised.

“CCLKR register” of Figure 7.7 is partly revised.

Section “7.1 Main clock” is partly revised.

Figure 7.4.1 is partly revised.

Section “7.5 CPU Clock and Peripheral Function Clock” and “7.5.2 Peripheral

Function Clock” are partly revised.

Section “7.7 System Clock Protective Function” and “7.8 Oscillation Stop and Re-

oscillation Detect Function” are partly revised.

Figure 8.1 is partly revised.

Figure 9.3.1 is partly revised.

IFSR2A registerin Figure 9.3.2 is partly revised.

Section “9.3.2 IR Bit” is partly revised.

Section “9.4 Interrupt Sequence” is partly revised.

Section “9.4.1 Interrupt Response Time” and Figure9.4.1.1 are partly revised.

Section “9.6 INT Interrupt” is partly revised.

Section “9.9 CAN0 Wake-up Interrupt” is partly revised.

“Divide ratio” of Table 12.1.1.1 is partly revised.

102

“8-bit PWM” of Table 12.1.4.1 is partly revised.

106

“Timer Bi register” in Figure 12.2.3 is partly revised.

111

Section “12.2.4 A-D Trigger mode” and Table 12.2.4.1 are partly revised.

112

Figure 12.2.4.2 is partly revised.

115

Figure 12.3.2 is partly revised.

117

“Timer B2 interrupt occurences fequency set counter” in Figure 12.3.4 is partly

revised.

119

Figure 12.3.6 is partly revised.

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