M16CSLASH29 datasheet(111/499 Pages) RENESAS

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9. Interrupts

page 87

9.9 CAN0 Wake-up Interrupt

CAN0 wake-up interrupt occurs when a falling edge is input to CRX. The CAN0 wake-up interrupt is en-

abled when the PortEn bit is set to 1 (CTX/CRX function) and Sleep bit is set to 1(Sleep mode enabled) in

the C0CTLR register. Figure 9.13 shows the block diagram of the CAN0 wake-up interrupt.

Figure 9.13 CAN0 Wake-up Interrupt Block Diagram

9.10 Address Match Interrupt

An address match interrupt request is generated immediately before executing the instruction at the ad-

dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi

address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the

PC that is saved to the stack area varies depending on the instruction being executed (refer to “Saving

Registers

”).

(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one

of the methods described below to return from the address match interrupt.

• Rewrite the content of the stack and then use the REIT instruction to return.

• Restore the stack to its previous state before the interrupt request was accepted by using the POP or

similar other instruction and then use a jump instruction to return.

Table 9.6

shows the value of the PC that is saved to the stack area when an address match interrupt

request is accepted.

aFigure 9.14

shows registers AIER, RMAD0, and RMAD1.

Interrupt control circuit

C01WKIC register

CAN0 wake-up

interrupt request

CRX

PortEn bit in C0CTLR register

Sleep bit in C0CTLR register

M16C/29 데이터시트(PDF) 111 Page - Renesas Technology Corp