M16CSLASH29 datasheet(264/499 Pages) RENESAS

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15. A/D Converter

page 240

Figure 15.18 ADTRGCON Register in Simultaneous Sample Sweep Mode

Table 15.9 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode

TRG

HPTRG0

TRG1

TRIGGER

Software trigger

Timer B0 underflow (1)

Timer B2 or Timer B2 interrupt generation frequency setting

counter underflow (2)

ADTRG

NOTES:

1. A count can be started for Timer B2, Timer B2 interrupt generation frequency

setting counter underflow or the INT5 pin falling edge as count start

conditions of Timer B0.

2. Select Timer B2 or Timer B2 interrupt generation frequency setting counter

using the TB2SEL bit in the TB2SC register.

A/D Trigger Control Register (1)

Symbol

Address

After Reset

ADTRGCON 03D216

0016

Bit Name

Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D operation mode select

bit 2

SSE

AN0 trigger select bit

See Table 15.9

HPTRG1

AN1 trigger select bit

HPTRG0

Nothing is assigned. If necessary, set to 0.

When read, the content is 0

(b7-b4)

NOTE:

1. If ADTRGCON is rewritten during A/D conversion, the conversion result will be undefined.

DTE

1: Simultaneous sample sweep mode or

delayed trigger mode 0, 1

A/D operation mode select

bit 3

0: Other than delayed trigger mode 0, 1

Set to 0 in simultaneous sample sweep

mode

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