M16CSLASH29 datasheet(284/499 Pages) RENESAS

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16. MULTI-MASTER I2C bus INTERFACE

page 260

Figure 16.5 S10 Register

NOTES:

1. This bit is read only if it is used for the status check.

To write to this bit, refer to 16.9 START Condition Generation Method and 16.11 STOP Condition Generation

Method

2. Read only. If necessary, set to 0.

3. To write to these bits, refer to 16.9 START Condition Generation Method and 16.11 STOP Condition

Generation Method.

0: Bus free

1: Bus busy

0: Interrupt request issued

1: No interrupt request issued

0: Not detected

1: Detected

0: No address matched

1: Address matched

0: No general call detected

1: General call detected

0: Last bit = 0

1: Last bit = 1

Communication mode select

bits 0

Bus busy flag

I C bus interface interrupt

request bit

Arbitration lost detection flag

Slave address comparison flag

General call detecting flag

Last receive bit

MST

TRX

AAS

ADR0

LRB

Function

Bit Name

Bit Symbol

0001000X2

After Reset

02E816

Address

Symbol

S10

0: Receive mode

1: Transmit mode

b7 b6 b5 b4 b3 b2b1b0

RO(1)

RO(2)

RO(1)

RO(2)

RW(3)

0: Slave mode

1: Master mode

Communication mode select

bit 1

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